Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Configuration Specification

A configuration specification defines which entity and architecture is used in place of the instances of a single component during elaboration. A configuration specification may also patch up differences in the names and types of generics and ports for that single component.

Syntax

  for InstanceLabel, ... : ComponentName
    use WhatToUse
      [GenericMap]
      [PortMap];

  WhatToUse =  {either}
  entity EntityName[(ArchitectureName)]
  configuration ConfigurationName
  open
    

Where

architecture-is--begin-end block--begin-end generate--begin-end See Declaration

Rules

The instance labels in front of the component name can be replaced by others or all. Each component instance can be explicitly configured once only.

Tips

Configuration specifications are inflexible, because changing the configuration requires editing the architecture containing the configuration. It is usually better to use separate configuration declarations.

Example

  -- (See Configuration)
  architecture FullyBound of Top is
    component Blk
      port (A: in Int8; F: out Int8);
    end component;

    for B1: Blk use entity Work.Blk(RTL);

    for B2: Blk use entity Work.GateLevelBlk(Synth)
          port map (IP => To_Vector(A),
                    To_Int8(OP) => F);
  begin
    B1: Blk port map (A, F);
    B2: Blk port map (B, G);
  end FullyBound;
    

See Also

Configuration, Component, Entity, Architecture